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8 Mbit LPC Flash
A Microchip Technology Company
SST49LF080A
Data Sheet
Table 5: LPC Read Cycle
Field
Clock
Field
Contents
LAD[3:0]
Cycle
1
Name
START
LAD[3:0] 1
0000
Direction
IN
Comments
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized.
2
CYCTYPE
010X
IN
Indicates the type of cycle. Bits 3:2 must be “01b” for memory
+ DIR
cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is
reserved.
3-10
ADDRESS
YYYY
IN
Address Phase for Memory Cycle. LPC protocol sup-
ports a 32-bit address phase. YYYY is one nibble of the
entire address. Addresses are transferred most-signifi-
cant nibble fist. See Table 3 for address bits definition
and Table 4 for valid memory address range.
11
TAR0
1111
IN
In this clock cycle, the host has driven the bus to all 1s
then Float
and then floats the bus. This is the first part of the bus
“turnaround cycle.”
12
TAR1
1111 (float)
Float
The SST49LF080A takes control of the bus during this
then OUT
cycle
13
SYNC
0000
OUT
The SST49LF080A outputs the value 0000b indicating
that data will be available during the next clock cycle.
14
15
16
DATA
DATA
TAR0
ZZZZ
ZZZZ
1111
OUT
OUT
OUT
This field is the least-significant nibble of the data byte.
This field is the most-significant nibble of the data byte.
In this clock cycle, the SST49LF080A has driven the bus
then Float
to all 1s and then floats the bus. This is the first part of
the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float
The host takes control of the bus during this cycle
then IN
T5.0 25026
1. Field contents are valid on the rising edge of the present clock cycle.
CE#
LCLK
LFRAME#
Start
CYCTYPE
+
DIR
Address
TAR0
TAR1
Sync
Data
LAD[3:0]
0000b
010Xb
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12]
A[11:8]
A[7:4]
A[3:0]
1111b
Tri-State
0000b
D[3:0]
D[7:4]
TAR
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks
1 Clock Data Out 2 Clocks
1235 F04.0
Figure 5: LPC Read Cycle Waveform
?2011 Silicon Storage Technology, Inc.
11
DS25086A
11/11
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